The Finite-Difference Time-Domain (FDTD) method is currently a popular method of performing electromagnetic computation. The FDTD algorithm's relative simplicity and versatility make it a useful tool for simulation, but the benefits are partially offset by the memory and computational power demands. These demands limit the algorithm's practical usability, and are usually implemented on high performance workstations. The FDTD computational method involves a series of simple calculations over the field of interest, iterated over many time cycles. Using a single threaded processing model, this is usually implemented very inefficiently as a series of nested "for" loops.
I propose that this algorithm be accelerated in hardware using the inherently parallel nature of a field programmable gate array (FPGA) device. If code for an FDTD computational kernel is developed, this kernel can be instantiated multiple times per FPGA device to enable parallel processing. Furthermore, one can upgrade to a larger FPGA device to increase parallelism, or downgrade to a smaller device if less performance is required, all while using the same code base. If developed, the intellectual property of the code could be sold to hardware developers to tailor to their own needs. FDTD cards and development boards could also be developed and sold to academic and research institutions.
Applications for this device are numerous. An FPGA with PCIe bus capabilities could be used to accelerate a desktop workstation's FDTD simulations by orders of magnitude. A small radar system could employ this system to detect buried landmines by performing an inverse FDTD based on backscatter. This device could be used for real time radar imaging. This device can be used to reduce the size and complexity of any system requiring FDTD calculations. In short, if hardware acceleration of FDTD becomes available there are plenty of opportunities currently in place for improving the current state of FDTD simulation.