In the Internet of Things era, electronics with ultralow power consumption are greatly sought after. In order to implement a microprocessor, basic logic gates and computing blocks are required. We propose a runtime reprogrammable microresonatorbased device that can be used to implement a compact, reprogrammable multiinput logic gate and also the most compact full adder block ever presented.
The proposed proofofconcept device consists of a laterally actuated doublyclamped microbeam, biased with a DC voltage, with three fixed identical electrodes on each side of the beam, in which the logic inputs (DC voltages), applied at the four corner electrodes, electrostatically tune the resonance frequency of the beam. The middle electrodes are used for driving the resonator and sensing its output. The logic one is defined as the “onresonance” signal, while the logic zero is defined as the “offresonance” signal. We found out that the digital inputs containing the same number of ones (n) result in the same resonance frequency for the beam (fn). For four inputs, we have five different resonance frequencies corresponding to five different cases: all zeros (f0), single one (f1), two ones (f2), three ones (f3), and four ones (f4). COMSOL simulations were performed to optimize the design and the required DC voltage for proper separation of the different states.
In order to realize a 4input NOR gate, which is a logically complete gate and can be used to implement any logic function, an AC signal with frequency f0 is applied to the drive electrode. In this case, only theallzeros input state will set the resonance frequency of the beam to f0 and create a high output signal (onresonance). The rest of the input combinations will shift the beam’s resonance frequency to values different from f0 and will result in a low output signal (offresonance). Similarly, applying the frequency of allones case (f4) to the drive electrode will program the device to work as a 4input AND gate. Therefore, one microresonator device can be runtime reprogrammed to do the function of 8 transistors (for standard CMOS NOR gate) and 10 transistors (for standard CMOS AND gate), which significantly reduces the complexity of digital circuits.
To implement the full adder device which has two outputs (sum and carryout), two identical microresonator devices are used. The sum output is implemented by applying two frequencies to the same device (f1 and f3), as the sum output is high if the input contains an odd number of ones. Similarly, for the carryout, two frequencies f2 and f3 are applied to the drive electrodes. This technique reduces the complexity of the digital logic design significantly; as an example, for a 64 bit adder, only 128 microresonators are required, compared to more than 1500 transistors for standard CMOS architectures. Therefore, the area of a single bit full adder using the proposed technique can be reduced by 97% compared to a single bit mirror adders using 65nm CMOS technology with energy/operation in femtojoules and moderate operation speed up to 1 MHz.

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ABOUT THE ENTRANT

Name:Sally Ahmed

Type of entry:teamTeam members:Sally Ahmed
Saad Ilyas
Xuecui Zou
Nizar Jaber
Ren Li
Prof. Mohammad I. Younis
Prof. Hossein Fariborzi 
Software used for this entry:COMSOL for both concept verification and device optimization

Patent status:none